The architecture of a typical memory array is known in the art. Generally, a memory array includes a number of lines arranged as rows and columns. The rows of the array are commonly referred to as word lines and the columns as bit lines.
The word lines and bit lines overlap at what can be referred to as nodes. Situated at or near each node is a memory cell, which is generally some type of transistor. In a virtual ground architecture, a bit line can serve as either a source or drain line for the transistor (memory cell), depending on which memory cell is being program verified or read. For simplicity of discussion, a “read” can refer to either a read operation or a program verification operation.
Prior Art FIG. 1 is a representation of a portion of a memory array 5. For simplicity of illustration, only the columns (bit lines) of memory array 5 are shown. Also, only two blocks (Block 0 and Block 1) of memory array 5 are shown; it is understood that there are typically more than two blocks in a conventional memory array. These groups of blocks may be referred to as input/output (I/O) blocks, or simply “I/Os.” In general, an I/O includes some number of columns that are coupled (e.g., gated) to a single I/O pad or port. In one type of conventional memory array, there are 32 columns per block or I/O (N=32).
It should be noted that the columns shown by Prior Art FIG. 1 are the “metal-2” bit lines. Associated with each metal-2 bit line are two “metal-1” bit lines. With N=32, for example, there are 64 metal-1 bit lines per I/O, and memory array 5 can store 64 bits of information per word line per I/O. The use of terminology such as metal-1 bit lines and metal-2 bit lines is known in the art.
When reading a selected memory cell, a core voltage is applied to the word line corresponding to that cell, and the bit line corresponding to that cell is connected to a load (e.g., a cascode or cascode amplifier). In a memory array that utilizes a virtual ground architecture, all of the memory cells on the word line are subject to the core voltage. This can induce a leakage, or error, current along the word line, in effect causing an unwanted interaction between the memory cells on the word line. The leakage current, if of sufficient magnitude, may cause an error when reading the selected memory cell.
To minimize the interaction among memory cells on a word line and to reduce errors during reads, a technique commonly referred to as precharging is used. Precharging works by charging (applying an electrical load) to the column next to the column that corresponds to the memory cell being read. If the drain node and the precharge node are at about the same voltage, then the precharge has the effect of reducing the leakage current. Referring to Prior Art FIG. 1, to read a memory cell on column 1, for example, a precharge voltage is applied to column 2.
In the conventional art, memory array 5 may be coupled to a redundancy array (not shown). The redundancy array is essentially another block of memory that has the same number of rows as memory array 5, but fewer columns. The number of columns in the redundancy array is typically less than the number of columns in a block or I/O, although this is not necessarily always the case.
To simplify the discussion of how a redundancy array is employed, an example will be used in which the number of columns in the redundancy array is less than the number of columns in a block. Testing of memory array 5 may indicate that the memory cells along one of the columns in the memory array cannot be properly read. A defect, such as a short to ground, may have been introduced into the column during manufacturing, for example. The redundancy array is used as a replacement for the defective column as well as the other columns in the block that contains the defective column. The columns in memory array 5 that are replaced using the redundancy array may be referred to as the “redundancy window.” A redundancy window 6 is exemplified in Prior Art FIG. 1. According to the present example, redundancy window 6 is fixed in position and includes some number of columns less than the number of columns in Block 1. Instead of writing data to and reading data from the columns in redundancy window 6, the data are written to and read from the redundancy array. Thus, the memory cells in redundancy window 6 are not programmed.
The redundancy scheme just described can be problematic after memory array 5 has been repeatedly erased. When a sector of memory is erased, all of the memory cells in the sector are erased. “Y-select” decoding is common for all I/Os; as such, when Block 1 is erased, the memory cells in redundancy window 6 are also erased. Therefore, continuing with the example from above, the memory cells in redundancy window 6 are erased even though these memory cells have not been programmed. As a result, the memory cells in redundancy window 6 can become “over-erased.” With over-erasing, the resistance of the memory cells in redundancy window 6 is decreased, thereby increasing the leakage (error) current for those cells. This in turn can effect the reading of memory cells in the columns adjacent to redundancy window 6, in particular the memory cells immediately adjacent to redundancy window 6 (e.g., those memory cells in column N−1). For instance, the leakage current associated with column N may be large; when the precharge is applied to column N, it may not be large enough to compensate for the leakage current, which may cause an error when reading column N−1.
Accordingly, a redundancy scheme that eliminates or reduces errors when reading memory cells adjacent to the redundancy window would be an improvement over conventional redundancy schemes.